74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input      EN,
    input      S,
    input      R,
    output reg Q,  // Added 'reg'
    output reg Qn  // Added 'reg'
);

always @(*) begin
    if (EN) begin
        case ({S, R})
            2'b00 : begin Q <= Q;    Qn <= Qn;   end // Hold
            2'b01 : begin Q <= 1'b0; Qn <= 1'b1; end // Reset
            2'b10 : begin Q <= 1'b1; Qn <= 1'b0; end // Set
            default: begin Q <= 0;   Qn <= 1;   end
        endcase
    end
end
    
endmodule