74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);
	// Write your code here
    always@(EN or S or R) begin
        if(EN==1) begin
            if(S==1 && R==0) begin Q<=1; Qn<=0; end
            if(S==0 && R==1) begin Q<=0; Qn<=1; end
            if(S==0 && R==0) begin    end
            if(S==1 && R==1) begin Q<=0; Qn<=1; end
        end
        else begin   end
    end
endmodule