74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output reg Q,
    output Qn
);
	// Write your code here
assign Qn=~Q;
always@(*)begin
    Q=Q;
    if(EN)begin
    case({S,R})
    2'B00:Q=Q;
    2'B01:Q=1'B0;
    2'B10:Q=1'B1;
    default: Q=1'B0;
    endcase
    end
end
	
endmodule