74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output Q,
    output Qn
);
	// Write your code here
	reg Q_reg;
    reg Qn_reg;
    always @(*) begin
        if(EN == 0) begin
            Q_reg <= Q_reg;
            Qn_reg <= Qn_reg;
        end 
        else begin
            case ({S,R})
                2'b00:begin Q_reg <= Q_reg; Qn_reg <= Qn_reg; end
                2'b01:begin Q_reg <= 1'b0; Qn_reg <= 1'b1; end
                2'b10:begin Q_reg <= 1'b1; Qn_reg <= 1'b0;end
                2'b11:begin Q_reg <= 1'b0; Qn_reg <= 1'b1; end
            endcase
        end
    end
    assign Q = Q_reg;
    assign Qn = Qn_reg;
endmodule