74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);
always@(*) begin
    if(EN==0) begin
        Q<=Q;
        Qn<=Qn;
    end
    else
    case({EN,S,R})
    3'b100:begin
        Q<=Q;
        Qn<=Qn;
    end
    3'b110:begin
        Q<=1;
        Qn<=0;
    end
    
    3'b101:begin
        Q<=0;
        Qn<=1;
    end
    3'b111:begin
        Q<=0;
        Qn<=1;
    end
    
    default: begin Q<=Q;
    Qn<=Qn;
    end
    endcase
end

  
    
	
	
endmodule