74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output Q,
    output Qn
);
reg  q;
	// Write your code here
    always@(*)begin
        if(EN)begin
            case({S,R})
                2'b01,2'b11: q<=0;
                2'b10: q<=1;
                2'b00: q<=q;
            endcase
            end
        else
            q<=q;
    end
assign Q = q;
assign Qn = ~q;
endmodule