74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);
	always @(*) begin
        if (EN) begin
            if (S) begin
                if (R) begin
                    Q = 0;
                    Qn = 1;
                end else begin
                    Q = 1;
                    Qn = 0;
                end
            end else begin

                if (R) begin
                    Q = 0;
                    Qn = 1;

            end
        end
    end
    end
	
endmodule