74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output Q,
    output Qn
);
	// Write your code here
	reg Q_reg;
    // Write your code here
    always @(*) begin
        Q_reg = EN ? (1'b0 | ~R) & ( S | Q_reg ) : Q_reg;
    end

    assign Q = Q_reg;
    assign Qn = ~Q;
    
endmodule