74. Gated SR Latch
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module sr_latch_enable (
input EN,
input S,
input R,
output Q,
output Qn
);
reg q;
always @(*) begin
if(EN) begin
if (S && !R) q = 1;
else if(!S && R) q =0;
else if(S && R) q =0;
end
end
assign Q = q;
assign Qn = ~q;
endmodule
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