74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output Q,
    output Qn
);
    reg Q_reg;
    reg Qn_reg;

always @* begin
    if(EN)begin
        if (S && R) begin
            Q_reg  = 1'b0;
            Qn_reg = 1'b1;
        end else if (S && !R) begin
            Q_reg  = 1'b1;
            Qn_reg = 1'b0;
        end else if (!S && R) begin
            Q_reg  = 1'b0;
            Qn_reg = 1'b1;
        end
    end
    else begin
        Q_reg  = Q_reg;
        Qn_reg = ~Q_reg;

    end
end
assign Q  = Q_reg;
assign Qn = Qn_reg;


    

	// Write your code here
	
endmodule