74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);
	// Write your code here
	always @(*)begin
        if (EN)
           case ({S,R})
               2'b00: begin
                Q = Q;
                Qn =Qn;
               end
               2'b01: begin
                Q = 0;
                Qn = 1;
                end
               2'b10: begin
                Q = 1;
                Qn = 0;
                end
               2'b11: begin
                Q =0;
                Qn = 1;
                end
           endcase
        else begin
           Q=Q;
           Qn=Qn;
        end
    end


endmodule