74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output Q,
    output Qn
);
	// Write your code here
    reg Qreg,Qnreg;
	always @* begin 
        if(EN) begin 
            if(R & !S) begin Qreg=1'b0; Qnreg=1'b1;  end
            else if (S & !R) begin Qreg=1'b1; Qnreg=1'b0; end  
            else if(S & R) begin Qreg=1'b0; Qnreg=1'b1; end
        end
    end
    assign Q=Qreg;
    assign Qn=Qnreg;
endmodule