74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output Q,
    output Qn
);
    reg Q_reg, Qn_reg;

	always @(*) begin
        if (EN) begin
            case ({S, R})
                2'b01: {Q_reg, Qn_reg} = 2'b01;
                2'b10: {Q_reg, Qn_reg} = 2'b10;
                2'b11: {Q_reg, Qn_reg} = 2'b01;
            endcase
        end
    end

    assign Q  = Q_reg ;
    assign Qn = Qn_reg;
endmodule