74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);
	always @(EN, S, R) begin
        if (EN) begin
            if ( S & ~R ) begin
                Q = 1;
                Qn = 0;
            end else if (R) begin
                Q = 0;
                Qn = 1;
            end
        end
    end
endmodule