74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output Q,
    output Qn
);
	// Write your code here
	wire [2:0] sel;
    assign sel = {S,R};
    reg temp,tempn;
    always@* begin
        if(EN) begin
        case(sel)
        3'd0    : begin temp = temp;tempn = tempn; end
        3'd1    : begin temp = 0;tempn = 1; end
        3'd2    : begin temp = 1;tempn = 0; end
        3'd3    : begin temp = 0;tempn = 1; end
        endcase
        end
        //else if((!EN)&(!S)&R)  begin  temp = 1;tempn = 0;   end
        else begin  temp = temp;tempn = tempn;   end
    end
    assign Q = temp;
    assign Qn = tempn;
endmodule