74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);


    always@(*)begin
        if(EN)begin
            if(R) begin
                Q = 0;
                Qn = 1;
            end
            else if(S & ~R)begin
                Q = 1;
                Qn = 0;
            end
            else if(~S & ~R)begin
                Q = Q;
                Qn = Qn;
            end
            else begin
                Q = 0;
                Qn = 0;
            end

        end
        else begin
            Q = Q;
            Qn = Qn;

        end




    end

	
endmodule