74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output reg Q,
    output Qn
);
	// Write your code here
always@*begin
    if(EN) begin
    case({S,R})
    2'b00:Q=Q;
    2'b01:Q=0;
    2'b10:Q=1;
    2'b11:Q=0;
    endcase
    end
end
assign Qn=~Q;	
endmodule