74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);
	// Write your code here
    reg prev_Q;
    always @* begin
        if (EN) begin
            if (R == 1) begin
                Q <= 1'b0;
            end else if (S == 1) begin
                Q <= 1'b1;               
            end 
            Qn <= ~Q;
        end
    end
endmodule