74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output Q,
    output Qn
);
	// Write your code here
    reg Q_r, Qn_r;

    always @* begin
        if(EN) begin
            if(R) begin
                Q_r=1'b0;
            end else if(S & ~R) begin
                Q_r=1'b1;
            end
        end

        Qn_r = ~Q_r;
    end

    assign Q  = Q_r;
    assign Qn = Qn_r;
	
endmodule