74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  wire EN,
    input  wire S,
    input  wire R,
    output reg  Q,
    output wire Qn
);

always @(*) begin

    // Latch active only when EN=1
    if (EN) begin

        // Reset has highest priority
        if (R) begin
            Q = 1'b0;
        end

        // Set
        else if (S) begin
            Q = 1'b1;
        end

        // Hold condition:
        // S=0, R=0
        // no assignment -> latch inferred
    end

    // EN=0:
    // hold previous state
    // no assignment
end

// Complement output
assign Qn = ~Q;

endmodule