74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output Q,
    output Qn
);
reg Q0;
reg Qn0;

always @(*) begin
    if(EN) begin
        if (S && R) begin
            Q0 = 1'b0;
            Qn0 = 1'b1;
        end
        else if (S && !R) begin
            Q0 = 1'b1;
            Qn0 = 1'b0;
        end
        else if(!S && R) begin
            Q0 = 1'b0;
            Qn0 = 1'b1;
        end
    end
end
assign Q = Q0;
assign Qn = Qn0;
	
endmodule