74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);
	// Write your code here
    always @(*) begin
        if (EN) begin
            if (S&&~R) begin
                Q=1'b1;
                Qn=1'b0;
            end
            else if (~S&&R) begin
                Q=1'b0;
                Qn=1'b1;
            end
            else if (S&&R) begin
                Q=1'b0;
                Qn=1'b1;
            end
        end
    end

endmodule