74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);

reg [1:0]con ,res;
 

	// Write your code here
    always @(*) begin
        con = {S,R};
        if (EN) begin
            case(con)
            2'b10 : res = 2'b10;
            2'b01 : res = 2'b01 ;
            2'b11 : res = 2'b01;
            2'b00 : res = res ;
            endcase
        end

        else begin
            Q <= Q;
            Qn <= Qn ;
        end
        {Q,Qn} = res;
    end
endmodule