74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);

always @(*)begin
    if (EN)
    case ({S,R})
    2'b00:begin
        Q=Q;
        Qn=Qn;
    end
    2'b01:begin
        Q=1'b0;
        Qn=1'b1;
    end
    2'b10:begin
        Q=1'b1;
        Qn=1'b0;
    end
    2'b11:begin
        Q=1'b0;
        Qn=1'b1;
    end
    endcase
    else begin
        Q=Q;
        Qn=Qn;
    end
end
endmodule