74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output reg Q,
    output Qn
);
	// Write your code here
	assign Qn = ~Q;
    always@(*)begin
        if(EN)
        case({S,R})
        2'b00: Q<= Q;
        2'b01: Q<= 1'b0;
        2'b10: Q<= 1'b1;
        2'b11: Q<= 1'b0;
        endcase
        else
        Q<=Q;
    end

endmodule