74. Gated SR Latch

How do you plan to solve it?

n sr latch with enable

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output reg Q,
    output Qn
);
	// Write your code here
    always @(*) begin
        case ({S,R})
            2'b00 : Q = Q;
            2'b01 : Q = EN ? 1'b0 : Q;
            2'b10 : Q = EN ? 1'b1 : Q;
            2'b11 : Q = EN ? 1'b0 : Q;
        endcase
    end
    assign Qn = ~Q;
	
endmodule