74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output Q,
    output Qn
);
	// Write your code here
    reg Q_1;
    reg Qn_1;
    always@(*) begin
    if (EN == 1) begin
        if ( S && !R ) begin
            Q_1 = 1'b1;
            Qn_1 = 1'b0;
        end else if ( !S && R ) begin
            Q_1 = 1'b0;
            Qn_1 = 1'b1;
        end else if ( S && R) begin
            Q_1 = 1'b0;
            Qn_1 = 1'b1;
        end
    end
    end
    assign Q = Q_1;
    assign Qn = Qn_1;
	
endmodule