74. Gated SR Latch

How do you plan to solve it?

Shorter version as the official solution:

• no need to check S when R=1
• no need to maintain a reg for Qn

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output Q,
    output Qn
);
	reg Q_reg;
    
    always @* begin
        if (EN) begin
            if (S && !R) Q_reg = 1'b1; // Set
            else if (R) Q_reg = 1'b0; // Reset
        end
    end

    assign Q = Q_reg;
    assign Qn = ~Q_reg;
	
endmodule