74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output Q,
    output Qn
);
	// Write your code here
    reg q, qn;
	always @(*)
    begin
        if( EN )
        begin
            if( {S, R} == 2'b11 )
            begin
                q = 1'b0;
                qn = ~q;
            end
            if( {S,R} == 2'b01 )
            begin
                q = 1'b0;
                qn = ~q;
            end
            else if( {S, R} == 2'b10 )
            begin
                q = 1'b1;
                qn = ~q;
            end
        end
    end
    assign Q = q;
    assign Qn = qn;
endmodule