74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output Q,
    output Qn
);
    // Write your code here
    wire no_r, and_sr, r_en, s_en;

    // always @* begin
        and(r_en, EN, R);
        and(s_en, EN, S);
        not not_r(no_r, r_en);
        and and_snr(and_sr, s_en, no_r);
        nor q_r_qn(Q, r_en, Qn);
        nor qn_and_sr_q(Qn, and_sr, Q);

    
	
endmodule