74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);
    always @(*) begin 
        casez ({EN, S, R})
            3'b0??, 3'b100: begin 
                Q = Q;
                Qn = Qn;
            end
            3'b111, 3'b101: begin 
                Q = 1'b0;
                Qn = 1'b1;
            end 
            3'b110: begin 
                Q = 1'b1;
                Qn = 1'b0;
            end
        endcase
    end
	
endmodule