74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);
	// Write your code here
	always @(*) begin
     case (EN)
     
     1'b1: begin 
        if(S==0 && R==1) begin //reset
            Q=0; Qn=1;
        end
        else if(S==1 && R==0) begin //set
            Q=1; Qn=0;
     end 
        else if(S==0 && R==0) begin //hold
            Q=Q; Qn=Qn;
        end
        else if (S==1 && R==1) begin //reset
            Q=0; Qn=1;
        end
        
     end
     1'b0: begin
        Q=Q; Qn=Qn;
     end
     default: begin
        Q=0; Qn=1;
     end
     endcase 
    end  
endmodule