74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);

    always @(*) begin
        if (EN) begin
            if (R) begin
                Q  <= 0;
                Qn <= 1;
            end
            else if (S) begin
                Q  <= 1;
                Qn <= 0;
            end
            // else HOLD
        end
        // EN=0 → HOLD
    end

endmodule