74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output Q,
    output Qn
);
reg q_int;
reg qn_int;
	// Write your code here
    always @(*) begin
    if (EN) begin
        // Priority: Reset > Set > Hold
        if (R) begin
            // Reset (also handles S=1,R=1 illegal case)
            q_int = 1'b0;
            qn_int = 1'b1;
        end
        else if (S) begin
            // Set
            q_int = 1'b1;
            qn_int = 1'b0;
        end
        // else: S=0, R=0 → Hold (no assignment)
    end
    // else: EN = 0 → Hold (no assignment)
end
assign Q  = q_int;
assign Qn = qn_int;
	
endmodule