74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output Q,
    output Qn
);
reg q, qn;
	// Write your code here
	always @* begin 
        if(EN) begin
        if( S && R) begin 
            q=1'b0;
            qn=1'b1;
        end
        else if( S && !R) begin 
            q=1'b1;
            qn=1'b0;
        end
        else if( !S && R) begin 
            q=1'b0;
            qn=1'b1;
        end
        end
    end
    assign Q=q;
    assign Qn=qn;
endmodule