74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  wire EN,
    input  wire S,
    input  wire R,
    output reg Q,
    output reg Qn
);
	// Write your code here
 always @(*) begin
if(EN)begin
    case({S,R})
    2'b10:begin  //set
        Q=1'b1;
        Qn=1'b0;
    end
    2'b01:begin //rest
    Q=1'b0;
    Qn=1'b1;
    end
    2'b00:begin //hold
    Q=Q;
    Qn=Qn;
    end
    2'b11: begin //invalid
    Q=1'b0;
    Qn=1'b1;
    end
    endcase
end






 end


	
endmodule