74. Gated SR Latch

How do you plan to solve it?

module sr_latch_enable (
    input  EN,
    input  S,
    input  R,
    output Q,
    output Qn
);
    // Write your code here
    reg qi;
    always @* begin
        if(EN) begin
            if(R) qi = 0;
            else if((~R)&S) qi = 1;
            else if((~S)&(~R)) qi = Q;
        end else if(~EN) qi = Q;

    end

    assign Q = qi;
    assign Qn = ~qi;

endmodule