module jk_ff_enable (
input CLK,
input EN,
input J,
input K,
output reg Q
);
always @(posedge CLK)begin
if(EN)begin
if(J == 0 && K == 0)
Q <= Q ;
else if(J == 0 && K == 1)
Q <= 0 ;
else if(J == 1 && K == 0)
Q <= 1 ;
else if(J == 1 && K == 1)
Q <= ~Q ;
end
else
Q <= Q ;
end
endmodule