82. JK Flip-Flop with Enable

How do you plan to solve it?

module jk_ff_enable (
    input  CLK,
    input  EN,
    input  J,
    input  K,
    output reg Q
);

wire [1:0] cmd = {J,K}; 

always @(posedge CLK) begin
    if (EN) begin
        case (cmd)
            2'b00 : Q <= Q;    // Hold
            2'b01 : Q <= 1'b0; // Reset
            2'b10 : Q <= 1'b1; // Set
            2'b11 : Q <= ~Q;   // Toggle
            default: Q <= Q;   // Good practice for synthesis
        endcase
    end
end


endmodule