module jk_ff_enable (
input CLK,
input EN,
input J,
input K,
output reg Q
);
always @(posedge CLK) begin
if(EN == 0)
Q <= Q;
else begin
if (J == 0 && K == 0)
Q <= Q; // giữ nguyên
else if (J == 0 && K == 1)
Q <= 1'b0; // reset
else if (J == 1 && K == 0)
Q <= 1'b1; // set
else
Q <= ~Q; // toggle
end
end
endmodule