82. JK Flip-Flop with Enable

How do you plan to solve it?

module jk_ff_enable (
    input  CLK,
    input  EN,
    input  J,
    input  K,
    output reg Q
);
always @(posedge CLK) begin
    if (EN) begin
        if (J) begin
            if (K) begin
                Q <= ~Q;
            end else begin
                Q <= 1;
            end
        end else begin
            if (K) begin
                Q <= 0;
            end else begin
                Q <= Q;
            end
        end
    end
end


endmodule