82. JK Flip-Flop with Enable

How do you plan to solve it?

module jk_ff_enable (
    input  CLK,
    input  EN,
    input  J,
    input  K,
    output reg Q
);
always @(posedge CLK) begin
    if (EN) begin
        if (!J && K) Q <= 1'b0;
        else if (J && !K) Q <= 1'b1;
        else if (J && K) Q <= ~Q;
    end
end
endmodule