82. JK Flip-Flop with Enable

How do you plan to solve it?

module jk_ff_enable (
    input  CLK,
    input  EN,
    input  J,
    input  K,
    output reg Q
);
// Write your code here
reg d, prev_q;
wire [1:0] jk;

assign jk = {J, K};
always @ (*) begin
prev_q = Q;
case(jk)
2'b00: begin
    d = Q;
end
2'b01: begin
    d = 1'b0;
end
2'b10: begin
    d = 1'b1;
end
2'b11: begin
    d = ~Q;
end
default: begin 
    d = Q;
end
endcase 
end

always @(posedge CLK) begin
    if (EN == 1'b0) begin
        Q <= prev_q;
    end else begin
        Q <= d;
    end
end


endmodule