82. JK Flip-Flop with Enable

How do you plan to solve it?

module jk_ff_enable (
    input  CLK,
    input  EN,
    input  J,
    input  K,
    output reg Q
);
// Write your code here
always @(posedge CLK) begin
    if(EN) begin
    if(~J&&K) begin
        Q<=0;
    end
    else if(J&&~K) begin
        Q<=1;
    end
    else if(J&&K) begin
        Q<=~Q;
    end
    end
end



endmodule