82. JK Flip-Flop with Enable

How do you plan to solve it?

module jk_ff_enable (
    input  CLK,
    input  EN,
    input  J,
    input  K,
    output reg Q
);
always@(posedge CLK)
begin 
    if(EN)
    Q<=(J&(~Q))|((~K)&Q);
    else
    Q<=Q;
end 


endmodule