82. JK Flip-Flop with Enable

How do you plan to solve it?

module jk_ff_enable (
    input  CLK,
    input  EN,
    input  J,
    input  K,
    output reg Q
);
    always@(posedge CLK) begin
        if(EN)begin
            case({J,K})
                2'b00 : Q <= Q;
                2'b01 : Q <= 0;
                2'b10 : Q <= 1;
                2'b11 : Q <= ~Q;
            endcase
        end
    end 
endmodule