82. JK Flip-Flop with Enable

How do you plan to solve it?

module jk_ff_enable (
    input  CLK,
    input  EN,
    input  J,
    input  K,
    output reg Q
);
// Write your code here
    wire q1;
    assign q1 = J ? (K ? ~Q : 1) : (K ? 0 : Q);
    always @(posedge CLK or posedge J or posedge K or negedge EN)
        if (!EN)
            Q <= Q;
        else Q <= q1;

endmodule