81. JK Flip-Flop

module jk_ff (
    input  CLK,
    input  J,
    input  K,
    output reg Q
);
    always @(posedge CLK) begin
        case ({J, K})
            2'b00: Q <= Q;       // hold
            2'b01: Q <= 1'b0;    // reset
            2'b10: Q <= 1'b1;    // set
            2'b11: Q <= ~Q;      // toggle
        endcase
    end
endmodule

💡Remember

• Use a case on {J,K} inside a clocked always block for clarity.
• Nonblocking (<=) ensures the toggle uses the pre-edge value of Q and avoids races when chaining flops.
• Inputs J/K only affect Q at the clock edge; between edges the state holds.
• Without an explicit reset, power-up is unknown; tests should tolerate X until the first qualifying edge.