1. Memory Module Select

Design a combinational logic circuit that replicates the address-decoding behavior required to activate a specific memory module on a motherboard. The circuit must monitor two control signals—the Address Match line and the Read Enable line—and assert the output high if and only if both signals are simultaneously asserted.

Constraints

• You must utilize exactly two input sources: Address Match and Read Enable.
• The output must remain low if the address does not match or if the Read Enable signal is inactive.
• To adhere to system architecture requirements, the activation logic must be synthesized using a restricted set of primitive logic components. You are strictly forbidden from using standard AND gate components.

Behavioral Reference