Multiple Drivers

November 26, 2025

Solving Approach

How do you plan to solve it?

Two assings for the same output. But this is not correct because you only can drive one signal in the time.

Code

module top_module (
    input a,
    input b,
    output y
);
    assign y = a;
    assign y = b;

endmodule

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Testbench Code

`timescale 1ns/1ps

module tb;
  // Inputs
  reg a, b;
  // Outputs
  wire y;
  // Expected Outputs
  reg expected_y;

  // Mismatch signal
  wire mismatch = (y !== expected_y);

  // DUT
  top_module dut(.a(a), .b(b), .y(y));

  integer TOTAL, PASS, FAIL;

  task run_case(input _a, input _b);
    begin
      a = _a; b = _b;
      expected_y = (_a === _b) ? _a : 1'bx; // golden model
      #5;
      TOTAL++;
      if (!mismatch) PASS++; else FAIL++;
      $display("a=%b b=%b | y=%b | expected_y=%b | mismatch=%b",
               a, b, y, expected_y, mismatch);
    end
  endtask

  initial begin
    $dumpfile("tb.vcd");
    $dumpvars(0, tb.a, tb.b, tb.y, tb.expected_y, tb.mismatch);

    TOTAL=0; PASS=0; FAIL=0;

    run_case(0,0);
    run_case(0,1);
    run_case(1,0);
    run_case(1,1);

    $display("======================================");
    $display("TOTAL_TEST_CASES=%0d", TOTAL);
    $display("TOTAL_PASSED_TEST_CASES=%0d", PASS);
    $display("TOTAL_FAILED_TEST_CASES=%0d", FAIL);
    $display("ALL_TEST_CASES_PASSED=%s", (FAIL==0) ? "true" : "false");
    $display("======================================");
    $finish;
  end
endmodule